MTL storage cells made from a pair of cross-coupled inverter stages are already well known. An example of such a memory cell is shown in IBM Technical Disclosure Bulletin, Vol. 21, No. 1, June, 1978, p. 231, in an article entitled "MTL Storage Cell" by S. K. Wiedmann. The equivalent circuit of the prior art storage cell is identical with the equivalent circuit of the memory cell of the present application. However, the injection zones of the basic structure are arranged laterally of the inverting transistor structures which with switching transistors form the inverter stages. The injection zones are each connected to a separate bit-line via a pair of contacts for each memory cell. Because the injectors are laterally positioned with respect to the vertically arranged inverting transistor, the areal requirements are greater than if the inverter stages were totally vertically arranged as taught by the present application. The memory cell of the present application which includes a pair of totally vertical arranged inverter stages, has areal requirements which are approximately half those of the prior art memory cell. This results from the use of a pair of inverter stages each of which has a vertically arranged injector requiring only two contacts per pair of injectors which are common bit-lines to a plurality of memory cells in the same column of a memory array. Finally, all the elements of the prior art inverter stages are formed by masking and then diffusing appropriate dopants into a single layer of semiconductor material. This process requires very tight alignment tolerances to achieve even the densities which can be obtained. The present process does not suffer from strict mask alignment tolerances inasmuch as certain of the process steps result in self-aligned regions which avoid the use of masks entirely.
U.S. Pat. No. 4,087,900, filed Oct. 18, 1976, entitled "Fabrication of Semiconductor Integrated Circuit Structure Including Injection Logic Configuration Compatible With Complementary Bipolar Transistors Utilizing Simultaneous Formation of Device Regions" discloses a process whereby both the switching transistor and the current source transistor are of the vertical type. To the extent that the contacts to the vertical structure shown are all at the surface of a semiconductor layer and that semiconductor regions are used for isolation zones, the structure and method of fabrication of the vertical complementary bipolar transistors are completely different from the structure and method of fabrication of the circuit arrangements of the present application.
U.S. Pat. No. 3,912,555, filed Sept. 18, 1973 and entitled "Semiconductor Integrated Circuit and Method for Manufacturing the Same" shows an NPN transistor and a PNP transistor formed in a common semiconductor chip in a vertical type arrangement. Both transistors have buried collector layers each being under a base area. While this reference suggests that complementary type transistors are formed in a vertical type arrangement, both the NPN and PNP transistor are formed in separate areas and do not form a vertical inverter circuit of the type disclosed in the present application. In other words, the circuit does not use a pair MTL inverters to form a memory cell nor does it use a process which includes the forming of dielectric isolation.
Accordingly, it is a principal object of the present invention to provide vertical, complementary bipolar transistors circuits in which all the regions of the transistor pairs are isolated from corresponding regions of another similar pair of transistors.
It is another object of the present invention to provide vertical, complementary bipolar transistors which when interconnected form a memory cell which is two times smaller than known memory cells.
It is another object of the present invention to provide a memory cell the buried injectors of which act as bit-lines for the memory cell.
It is another object of the present invention to provide a method of fabricating buried injector memory cells, the injectors of which are isolated from each other and from adjacent injectors by dielectric isolation regions.
Still another object of the present invention is to provide a process for fabricating memory cells formed from vertical, complementary, bipolar transistor circuits. The buried injectors, single crystal regions and associated polycrystalline regions of which are self-aligned as a result of the presence of dielectric regions.